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RISC-V China Summit Showcases Domestic Compute Breakthrough: Server-Grade "V100" Chip Debu

   2026-10-22 Securities Times / Securities 50

At the 6th RISC-V China Summit in Shenzhen (October 18-20), over 450 exhibitors gathered as domestic chip firms rallied around the open-source instruction set to break through in AI compute, Securities Daily reported on October 22. SpacemiT and the Chines

At the 6th RISC-V China Summit in Shenzhen (October 18-20), over 450 exhibitors gathered as domestic chip firms rallied around the open-source instruction set to break through in AI compute, Securities Daily reported on October 22. SpacemiT and the Chinese Academy of Sciences' XiangShan team released the V100, the industry's first general compute chip fully meeting server specifications.

V100 tackles server-scene binary-compatibility, letting the chip drop into existing data centers without per-chip OS customization; its key IP is self-developed after about three years, with general-compute, AI-compute and storage server models launched together. "V100 means RISC-V formally steps into the scalable data-center market," said SpacemiT CEO Chen Zhijian.

Alibaba's Damo Academy published a vehicle-grade processor and said its XuanTie cores have stably shipped over 6 billion units; UREX showed high-performance cores and edge-AI clusters supporting model inference and robot debugging. The Beijing Institute of Open Source Silicon noted the industry's center of gravity is shifting fast from embedded controllers to mid-high-end and server-class chips.

RISC-V's fully open, extensible design breaks closed-license barriers and gives Chinese firms a new track to master open architecture — well matched to the country's complete electronics supply chain and rich embodied-AI and robotics scenarios.

Source: Securities Times / Securities Daily

 
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