Samsung Unveils HBM5 Roadmap: 2nm Chip, 12-Layer Stack, 2x Performance

Samsung Electronics unveiled its next-generation memory technology roadmap at SEMICON Taiwan 2026 on September 1, 2026. The HBM5 specification targets a 2nm-based foundational chip with 12-layer, 16-layer, and 20-layer DRAM stacking options. Samsung stated that HBM5 aims to achieve 2x the performance of HBM4E, with a 20% improvement in per-watt performance and a 20% reduction in thermal resistance. Mass production is targeted for approximately 2028. Samsung also announced its zHBM (zero-change HBM) architecture, a new memory design optimized for AI workloads with significantly reduced power consumption, with production expected after 2029. The roadmap underscores Samsung's strategy to compete with SK Hynix and Micron in the high-bandwidth memory market critical for AI training and inference hardware. Samsung added that its HBM5 products will be fully compatible with upcoming GPU and AI accelerator platforms from major semiconductor manufacturers.